The present invention relates to balanced phase detector circuits and, more particularly, to a low offset commutating phase detector suited for use in a phase locked loop.
Phase detectors are well known in the art. Typically, such phase detectors are comprised of a balanced analog multiplier input section, a current turn-around circuit coupled to the outputs of the multiplier section and a differential-to-single ended converter circuit for supplying a single output signal in response to a pair of input signals being applied to respective inputs of the multiplier section. The phase detector generates the well known S-shaped transfer function as the phase of the two input signals are varied with respect to one another with the output of the detector being zero whenever the two input signals are in phase quadrature.
When fabricated in monolithic integrated circuit form, prior art phase detectors, as discussed above, produce phase errors which can not be tolerated in precision phase lock loops. These phase errors are generated in the current turn-around and current mirror or differential-to-single ended converter circuitry due to mismatch between transistors and resistors comprising these circuits.
Hence, a need exists for an improved phase detector circuit having very low offset to eliminate such phase errors.